The Inter-Integrated Circuit serial bus, which may also be referred to as the I2C bus or the I2C bus, is a serial single-ended computer bus that was intended for use in connecting low-speed peripherals to a processor. The I2C bus is a multi-master bus in which each device can serve as a master and a slave for different messages transmitted on the I2C bus. The I2C bus can transmit data using only two bidirectional open-drain connectors, including a Serial Data Line (SDA) and a Serial Clock Line (SCL). The connectors typically include signal wires that are terminated by pull-up resistors.
Protocols governing I2C bus operations define basic types of messages, each of which begins with a START and ends with a STOP. The I2C bus uses 7-bit addressing and defines two types of nodes. A master node is a node that generates the clock and initiates communication with slave nodes. A slave node is a node that receives the clock and responds when addressed by the master. The I2C bus is a multi-master bus, which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (i.e., after a STOP is sent).
In the context of a camera implementation, unidirectional transmissions may be used to capture an image from a sensor and transmit such image data to memory in a baseband processor, while control data may be exchanged between the baseband processor and the sensor as well as other peripheral devices. In one example, a Camera Control Interface (CCI) protocol may be used for such control data between the baseband processor and the image sensor (and/or one or more slave nodes). In one example, the CCI protocol may be implemented over an I2C serial bus between the image sensor and the baseband processor. A CCI extended (CCIe) protocol has been defined to extend the throughput over the I2C bus.
Within the CCIe protocol, interrupts are used to allow a slave node to indicate to the master node that it wishes to use the bus. A mechanism is needed to permit slave nodes to send such interrupts to the master node. Traditional I2C or Camera Control Interface based camera systems use separate interrupt (IRQ) lines for each slave node, which increases device cost due to the large number of pins. The concept of a separate interrupt pin for each slave node means that each slave node must have a single dedicate interrupt pin.
Consequently, it would be desirable to eliminate the use of dedicated interrupt pins in master and slave nodes sharing a bus for CCIe implementations.